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3.75 Gbps Quad Bidirectional CX4 Equalizer ADN8102
FEATURES
Optimized for dc to 3.75 Gbps data Programmable input equalization Up to 22 dB boost at 1.875 GHz Compensates up to 30 meters of CX4 cable up to 3.75 Gbps Compensates up to 40 inches of FR4 up to 3.75 Gbps Programmable output pre-emphasis/de-emphasis Up to 12 dB boost at 1.875 GHz (3.75 Gbps) Compensates up to 15 meters of CX4 cable up to 3.75 Gbps Compensates up to 40 inches of FR4 up to 3.75 Gbps Flexible 1.8 V to 3.3 V core supply Per lane P/N pair inversion for routing ease Low power: 125 mW/channel up to 3.75 Gbps DC- or ac-coupled differential CML inputs Programmable CML output levels 50 on-chip termination Loss-of-signal detection Temperature range operation: -40C to +85C Supports 8b10b, scrambled, or uncoded NRZ data I2C control interface 64-lead LFSCP (QFN) package
LOS_B RECEIVE EQUALIZATION Ix_B[3:0] EQ 2:1
FUNCTIONAL BLOCK DIAGRAM
ADN8102
TRANSMIT PRE-EMPHASIS
PE
Ox_B[3:0]
LB TRANSMIT PRE-EMPHASIS Ox_A[3:0] PE 2:1 RECEIVE EQUALIZATION EQ
LOS_A
Ix_A[3:0]
ADDR[1:0] SCL SDA RESET
CONTROL LOGIC
Figure 1.
GENERAL DESCRIPTION
The ADN8102 is a quad bidirectional CX4 cable/backplane equalizer with eight differential PECL-/CML-compatible inputs with programmable equalization and eight differential CML outputs with programmable output levels and pre-emphasis or de-emphasis. The operation of this device is optimized for NRZ data at rates up to 3.75 Gbps. The receive inputs provide programmable equalization to compensate for up to 30 meters of CX4 cable (24 AWG) or 40 inches of FR4, and programmable pre-emphasis to compensate for up to 15 meters of CX4 cable (24 AWG) or 40 inches of FR4 at 3.75 Gbps. Each channel also provides programmable loss-ofsignal detection and loopback capability for system testing and debugging. The ADN8102 is controlled through toggle pins, an I2C(R) control interface that provides more flexible control, or a combination of both. Every channel implements an asynchronous path supporting dc to 3.75 Gbps NRZ data, fully independent of other channels. The ADN8102 has low latency and very low channel-to-channel skew. The main application for the ADN8102 is to support switching in chassis-to-chassis applications over CX4 or InfiniBand(R) cables. The ADN8102 is packaged in a 9 mm x 9 mm 64-lead LFCSP (QFN) package and operates from -40C to +85C.
APPLICATIONS
10GBase-CX4 HiGigTM InfiniBand 1x, 2x Fibre Channel XAUI Gigabit Ethernet over backplane or cable CPRITM 50 cables
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2008 Analog Devices, Inc. All rights reserved.
07060-001
EQ_A[1:0] PE_A[1:0] EQ_B[1:0] PE_B[1:0] ENA ENB
ADN8102 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Specifications .................................................................. 5 Absolute Maximum Ratings............................................................ 6 ESD Caution .................................................................................. 6 Pin Configuration and Function Descriptions ............................. 7 Typical Performance Characteristics ............................................. 9 Theory of Operation ...................................................................... 16 Introduction ................................................................................ 16 Receivers ...................................................................................... 16 Equalization Settings .................................................................. 17
2
Lane Inversion ............................................................................ 18 Loopback ..................................................................................... 19 Transmitters ................................................................................ 20 Selective Squelch and Disable ................................................... 25 I C Control Interface ...................................................................... 26 Serial Interface General Functionality..................................... 26 I2C Interface Data Transfers--Data Write .............................. 26 I2C Interface Data Transfers--Data Read ............................... 27 PCB Design Guidelines ................................................................. 28 Power Supply Connections and Ground Planes .................... 28 Transmission Lines..................................................................... 28 Soldering Guidelines for Chip Scale Package ............................. 28 Register Map ................................................................................... 29 Outline Dimensions ....................................................................... 31 Ordering Guide .......................................................................... 31
REVISION HISTORY
8/08--Rev. 0 to Rev. A Changes to Features Section............................................................ 1 Changes to Loss of Signal/Signal Detect Section ....................... 18 Added Recommended LOS Settings Section .............................. 18 Deleted Figure 39; Renumbered Sequentially ............................ 18 Exposed Paddle Notation Added to Outline Dimensions ........ 31 5/08--Revision 0: Initial Version
Rev. A | Page 2 of 32
ADN8102 SPECIFICATIONS
VCC = 1.8 V, VEE = 0 V, VTTI = VTTO = VCC, RL = 50 , differential output swing = 800 mV p-p differential, 3.75 Gbps, PRBS 27 - 1, TA = 25C, unless otherwise noted. Table 1.
Parameter DYNAMIC PERFORMANCE Maximum Data Rate/Channel (NRZ) Deterministic Jitter Random Jitter Residual Deterministic Jitter With Input Equalization Conditions Min 3.75 Data rate < 3.75 Gbps; BER = 1 x 10-12 VCC = 1.8 V Data rate < 3.25 Gbps; 0 inches to 40 inches FR4 Data rate < 3.25 Gbps; 0 meters to 30 meters CX4 Data rate < 3.75 Gbps; 0 inches to 40 inches FR4 Data rate < 3.75 Gbps; 0 meters to 30 meters CX4 Data rate < 3.25 Gbps; 0 inches to 40 inches FR4 Data rate < 3.25 Gbps; 0 meters to 15 meters CX4 Data rate < 3.75 Gbps; 0 inches to 40 inches FR4 Data rate < 3.75 Gbps; 0 meters to 15 meters CX4 20% to 80% 33 1.5 0.20 0.19 0.24 0.21 0.13 0.37 0.14 0.41 75 1 50 Typ Max Unit Gbps ps p-p ps rms UI UI UI UI UI UI UI UI ps ns ps
With Output Pre-Emphasis
Output Rise/Fall Time Propagation Delay Channel-to-Channel Skew OUTPUT PRE-EMPHASIS Equalization Method Maximum Boost Pre-Emphasis Tap Range INPUT EQUALIZATION Minimum Boost Maximum Boost Number of Equalization Settings Gain Step Size INPUT CHARACTERISTICS Input Voltage Swing Input Voltage Range Input Resistance Input Return Loss OUTPUT CHARACTERISTICS Output Voltage Swing
1-tap programmable pre-emphasis 800 mV p-p output swing 200 mV p-p output swing Minimum Maximum EQBY = 1 Maximum boost occurs at 1.875 GHz
6 12 2 12 1.5 22 8 2.5 300 VEE + 0.4 VCC + 0.5 50 5 740 800 100 100 1300 1800 2000
dB dB mA mA dB dB dB mV p-p V p-p V p-p dB mV p-p mV p-p mV p-p mV p-p mV p-p mV p-p
Differential, VICM 1 = VCC - 0.6 V Single-ended absolute voltage level, VL minimum Single-ended absolute voltage level, VH maximum Single-ended Measured at 2.5 GHz DC, differential, PE = 0, default, VCC = 1.8 V DC, differential, PE = 0, default, VCC = 3.3 V DC, differential, PE = 0, minimum output level, 2 VCC = 1.8 V DC, differential, PE = 0, minimum output level,2 VCC = 3.3 V DC, differential, PE = 0, maximum output level,2 VCC = 1.8 V DC, differential, PE = 0, maximum output level,2 VCC = 3.3 V
45
55
635
870
Rev. A | Page 3 of 32
ADN8102
Parameter Output Voltage Range Conditions Single-ended absolute voltage level, TxHeadroom = 0; VL minimum Single-ended absolute voltage level, TxHeadroom = 0; VH maximum Single-ended absolute voltage level, TxHeadroom = 1; VL minimum Single-ended absolute voltage level, TxHeadroom = 1; VH maximum Minimum output current per channel Maximum output current per channel, VCC = 1.8 V Single-ended Measured at 2.5 GHz IN_A/IN_B THRESH = 0x0C IN_A/IN_B HYST = 0x0D Min Typ VCC - 1.1 VCC + 0.6 VCC - 1.2 VCC + 0.6 2 21 50 5 20 225 Max Unit V V V V mA mA dB mV diff mV diff
Output Current Output Resistance Output Return Loss LOS CHARACTERISTICS Assert Level Deassert Level POWER SUPPLY Operating Range VCC DVCC VTTI VTTO Supply Current VTTO VCC VEE LOGIC CHARACTERISTICS Input High, VIH Input Low, VIL Output High, VOH Output Low, VOL THERMAL CHARACTERISTICS Operating Temperature Range JA
1 2
43
57
VEE = 0 V VEE = 0 V, DVCC (VCC + 1.3 V) (VEE + 0.4 V + 0.5 x VID) < VTTI < (VCC + 0.5 V) (VCC - 1.1 V + 0.5 x VOD) < VTTO < (VCC + 0.5 V) All outputs enabled All outputs enabled All outputs enabled DVCC = 3.3 V
1.7 3.0 VEE + 0.4 VCC - 1.1
1.8 3.3 1.8 1.8 63 460 586
3.6 3.6 3.6 3.6 69 565
V V V V mA mA mA V V V V C C/W
2.5 1.0 2.5 1.0 -40 22 +85
VICM is the input common-mode voltage. Programmable via I2C.
Rev. A | Page 4 of 32
ADN8102
TIMING SPECIFICATIONS
Table 2. I2C Timing Parameters
Parameter fSCL tHD:STA tSU:STA tLOW tHIGH tHD:DAT tSU:DAT tR tF tSU:STO tBUF CIO Min 0 0.6 0.6 1.3 0.6 0 10 1 1 0.6 1 5 Max 400 N/A N/A N/A N/A N/A N/A 300 300 N/A N/A 7 Unit kHz s s s s s ns ns ns s ns pF Description SCL clock frequency Hold time for a start condition Setup time for a repeated start condition Low period of the SCL clock High period of the SCL clock Data hold time Data setup time Rise time for both SDA and SCL Fall time for both SDA and SCL Setup time for a stop condition Bus free time between a stop and a start condition Capacitance for each I/O pin
SDA
tF
tSU:DAT tLOW tR tF
tHD:STA
tR
tBUF
SCL
07060-010
tHD:STA
S
tHD:DAT
tHIGH
tSU:STA
Sr
tSU:STO
P S
Figure 2. I C Timing Diagram
2
Rev. A | Page 5 of 32
ADN8102 ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter VCC to VEE VTTI VTTO Internal Power Dissipation Differential Input Voltage Logic Input Voltage Storage Temperature Range Lead Temperature Rating 3.7 V VCC + 0.6 V VCC + 0.6 V 4.26 W 2.0 V VEE - 0.3 V < VIN < VCC + 0.6 V -65C to +125C 300C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
Rev. A | Page 6 of 32
ADN8102 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PE_A1 PE_A0 ENA OP_A0 ON_A0 VCC OP_A1 ON_A1 VTTO OP_A2 ON_A2 VEE OP_A3 ON_A3 ADDR1 ADDR0 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
RESET LOS_A IN_A0 IP_A0 VCC IN_A1 IP_A1 VTTI IN_A2 IP_A2 VEE IN_A3 IP_A3 DVCC EQ_A1 EQ_A0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
PIN 1 INDICATOR
ADN8102
TOP VIEW (Not to Scale)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
SCL SDA LOS_B IP_B0 IN_B0 VCC IP_B1 IN_B1 VTTI IP_B2 IN_B2 VEE IP_B3 IN_B3 EQ_B1 EQ_B0
VEE LB ON_B0 OP_B0 VCC ON_B1 OP_B1 VTTO ON_B2 OP_B2 VEE ON_B3 OP_B3 ENB PE_B1 PE_B0
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Mnemonic RESET LOS_A IN_A0 IP_A0 VCC IN_A1 IP_A1 VTTI IN_A2 IP_A2 VEE IN_A3 IP_A3 DVCC EQ_A1 EQ_A0 VEE LB ON_B0 OP_B0 VCC ON_B1 OP_B1 VTTO ON_B2 OP_B2 VEE Type Control Digital I/O I/O I/O Power I/O I/O Power I/O I/O Power I/O I/O Power Control Control Power Control I/O I/O Power I/O I/O Power I/O I/O Power Description Reset Input, Active Low Port A Loss of Signal Status, Active Low High Speed Input Complement High Speed Input Positive Supply High Speed Input Complement High Speed Input Input Termination Supply High Speed Input Complement High Speed Input Negative Supply High Speed Input Complement High Speed Input Digital Power Supply Port A Input Equalization MSB Port A Input Equalization LSB Negative Supply Loopback Control High Speed Output Complement High Speed Output Positive Supply High Speed Output Complement High Speed Output Output Termination Supply High Speed Output Complement High Speed Output Negative Supply
Rev. A | Page 7 of 32
07060-002
ADN8102
Pin No. 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 EP Mnemonic ON_B3 OP_B3 ENB PE_B1 PE_B0 EQ_B0 EQ_B1 IN_B3 IP_B3 VEE IN_B2 IP_B2 VTTI IN_B1 IP_B1 VCC IN_B0 IP_B0 LOS_B SDA SCL ADDR0 ADDR1 ON_A3 OP_A3 VEE ON_A2 OP_A2 VTTO ON_A1 OP_A1 VCC ON_A0 OP_A0 ENA PE_A0 PE_A1 EPAD Type I/O I/O Control Control Control Control Control I/O I/O Power I/O I/O Power I/O I/O Power I/O I/O Digital I/O Control Control Control Control I/O I/O Power I/O I/O Power I/O I/O Power I/O I/O Control Control Control Power Description High Speed Output Complement High Speed Output Port B Enable Port B Output Pre-Emphasis MSB Port B Output Pre-Emphasis LSB Port B Input Equalization LSB Port B Input Equalization MSB High Speed Input Complement High Speed Input Negative Supply High Speed Input Complement High Speed Input Input Termination Supply High Speed Input Complement High Speed Input Positive Supply High Speed Input Complement High Speed Input Port B Loss of Signal Status, Active Low I2C Control Interface Data Input/Output I2C Control Interface Clock Input I2C Control Interface Address LSB I2C Control Interface Address MSB High Speed Output Complement High Speed Output Negative Supply High Speed Output Complement High Speed Output Output Termination Supply High Speed Output Complement High Speed Output Positive Supply High Speed Output Complement High Speed Output Port A Enable Port A Output Pre-Emphasis LSB Port A Output Pre-Emphasis MSB EPAD Must Be Connected to VEE
Rev. A | Page 8 of 32
ADN8102 TYPICAL PERFORMANCE CHARACTERISTICS
DATA OUT 2 50 CABLES 2 INPUT PIN OUTPUT 2 PIN 50 CABLES 2 50 TP2
PATTERN GENERATOR
ADN8102
TP1 AC-COUPLED EVALUATION BOARD
HIGH SPEED SAMPLING OSCILLOSCOPE
07060-011
Figure 4. Standard Test Circuit (No Channel)
07060-012
200mV/DIV
200mV/DIV
50ps/DIV
50ps/DIV
Figure 5. 3.25 Gbps Input Eye (TP1 from Figure 4)
Figure 7. 3.25 Gbps Output Eye, No Channel (TP2 from Figure 4)
200mV/DIV
200mV/DIV
07060-013
50ps/DIV
50ps/DIV
Figure 6. 3.75 Gbps Input Eye (TP1 from Figure 4)
Figure 8. 3.75 Gbps Output Eye, No Channel (TP2 from Figure 4)
Rev. A | Page 9 of 32
07060-015
07060-014
ADN8102
DATA OUT 2 50 CABLES 2 FR4 TEST BACKPLANE 50 CABLES 2 2
200mV/DIV
INPUT OUTPUT 2 PIN PIN
50 CABLES 2 50 TP3
PATTERN GENERATOR
DIFFERENTIAL STRIPLINE TRACES TP1 8mils WIDE, 8mils SPACE, 8mils DIELECTRIC HEIGHT TRACE LENGTHS = 40''
ADN8102
TP2 AC-COUPLED EVALUATION BOARD
HIGH SPEED SAMPLING OSCILLOSCOPE
50ps/DIV REFERENCE EYE DIAGRAM AT TP1
Figure 9. Input Equalization Test Circuit, FR4
200mV/DIV
07060-017
200mV/DIV
50ps/DIV
50ps/DIV
Figure 10. 3.25 Gbps Input Eye, 40 Inch FR4 Input Channel (TP2 from Figure 9)
Figure 12. 3.25 Gbps Output Eye, 40 Inch FR4 Input Channel, Best EQ Setting (TP3 from Figure 9)
200mV/DIV
07060-018
200mV/DIV
50ps/DIV
50ps/DIV
Figure 11. 3.75 Gbps Input Eye, 40 Inch FR4 Input Channel (TP2 from Figure 9)
Figure 13. 3.75 Gbps Output Eye, 40 Inch FR4 Input Channel, Best EQ Setting (TP3 from Figure 9)
Rev. A | Page 10 of 32
07060-020
07060-019
07060-016
ADN8102
DATA OUT 2 50 CABLES 2 30m CX4 CABLE 50 CABLES 2 2 INPUT OUTPUT 2 PIN PIN 50 CABLES 2 50 TP3
200mV/DIV
PATTERN GENERATOR
ADN8102
TP1 TP2 AC-COUPLED EVALUATION BOARD
HIGH SPEED SAMPLING OSCILLOSCOPE
50ps/DIV REFERENCE EYE DIAGRAM AT TP1
Figure 14. Input Equalization Test Circuit, CX4
200mV/DIV
200mV/DIV
07060-022
50ps/DIV
50ps/DIV
Figure 15. 3.25 Gbps Input Eye, 30 Meters CX4 Cable (TP2 from Figure 14)
Figure 17. 3.25 Gbps Output Eye, 30 Meters CX4 Cable, Best EQ Setting (TP3 from Figure 14)
200mV/DIV
200mV/DIV
07060-023
50ps/DIV
50ps/DIV
Figure 16. 3.75 Gbps Input Eye, 30 Meters CX4 Cable (TP2 from Figure 14)
Figure 18. 3.75 Gbps Output Eye, 30 Meters CX4 Cable, Best EQ Setting (TP3 from Figure 14)
Rev. A | Page 11 of 32
07060-025
07060-024
07060-021
ADN8102
DATA OUT 2 50 CABLES 2 50 CABLES 2 INPUT OUTPUT 2 PIN PIN FR4 TEST BACKPLANE 2 50 CABLES 2 50 TP3
200mV/DIV
PATTERN GENERATOR
ADN8102
TP1 AC-COUPLED EVALUATION BOARD
DIFFERENTIAL STRIPLINE TRACES TP2 8mils WIDE, 8mils SPACE, 8mils DIELECTRIC HEIGHT TRACE LENGTHS = 40''
HIGH SPEED SAMPLING OSCILLOSCOPE
50ps/DIV REFERENCE EYE DIAGRAM AT TP1
Figure 19. Output Pre-Emphasis Test Circuit, FR4
200mV/DIV
07060-027
200mV/DIV
50ps/DIV
50ps/DIV
Figure 20. 3.25 Gbps Output Eye, 40 Inch FR4 Output Channel, PE = 0 (TP3 from Figure 19)
Figure 22. 3.25 Gbps Output Eye, 40 Inch FR4 Output Channel, PE = Best Setting (TP3 from Figure 19)
07060-028
200mV/DIV
200mV/DIV
50ps/DIV
50ps/DIV
Figure 21. 3.75 Gbps Output Eye, 40 Inch FR4 Output Channel, PE = 0 (TP3 from Figure 19)
Figure 23. 3.75 Gbps Output Eye, 40 Inch FR4 Output Channel, PE = Best Setting (TP3 from Figure 19)
Rev. A | Page 12 of 32
07060-030
07060-029
07060-026
ADN8102
DATA OUT 2 50 CABLES 2 INPUT OUTPUT 2 PIN PIN 50 CABLES 2 15m CX4 CABLE 2 50 CABLES 2 50 TP2 TP3
200mV/DIV
PATTERN GENERATOR
ADN8102
TP1 AC-COUPLED EVALUATION BOARD
HIGH SPEED SAMPLING OSCILLOSCOPE
07060-031
50ps/DIV REFERENCE EYE DIAGRAM AT TP1
Figure 24. Output Pre-Emphasis Test Circuit, CX4
50mV/DIV
50mV/DIV
07060-032
50ps/DIV
50ps/DIV
Figure 25. 3.25 Gbps Output Eye, 15 Meters CX4 Cable, PE = 0 (TP3 from Figure 24)
Figure 27. 3.25 Gbps Output Eye, 15 Meters CX4 Cable, PE = Best Setting (TP3 from Figure 24)
50mV/DIV
50mV/DIV
07060-033
50ps/DIV
50ps/DIV
Figure 26. 3.75 Gbps Output Eye, 15 Meters CX4 Cable, PE = 0 (TP3 from Figure 24)
Figure 28. 3.75 Gbps Output Eye, 15 Meters CX4 Cable, PE = Best Setting (TP3 from Figure 24)
Rev. A | Page 13 of 32
07060-035
07060-034
ADN8102
80 70 60 50 40 30 20 10
07060-036
100
DETERMINISTIC JITTER (ps)
DETERMINISTIC JITTER (ps)
80
60
40 VCC = 1.8V
VCC = 3.3V
20
0
20 DATA RATE (Hz)
40
60
1.5
2.0 2.5 3.0 INPUT COMMON MODE (V)
3.5
4.0
Figure 29. Deterministic Jitter vs. Data Rate
Figure 32. Deterministic Jitter vs. Input Common Mode
100 90
100
DETERMINISTIC JITTER (ps)
70 60 50 40 30 20 10
07060-037
DETERMINISTIC JITTER (ps)
80
80
60
40
20
0
0.5
1.0 1.5 2.0 DIFFERENTIAL INPUT SWING (V)
2.5
1.5
2.0
2.5 VCC (V)
3.0
3.5
4.0
Figure 30. Deterministic Jitter vs. Differential Input Swing
Figure 33. Deterministic Jitter vs. Supply Voltage
100
100
DETERMINISTIC JITTER (ps)
80
60
DETERMINISTIC JITTER (ps)
80
60 VCC = 1.8V 40 VCC = 3.3V 20
40
20
07060-038
-40
-20
0 20 40 TEMPERATURE (C)
60
80
100
1.5
2.0
2.5 VTTO (V)
3.0
3.5
4.0
Figure 31. Deterministic Jitter vs. Temperature
Figure 34. Deterministic Jitter vs. Output Termination Voltage
Rev. A | Page 14 of 32
07060-041
0 -60
0 1.0
07060-040
0
0 1.0
07060-039
0
0 1.0
ADN8102
450000 400000 350000 90 100
NUMBER OF SAMPLES
300000
tR/tF (ps)
250000 200000 150000 100000 50000
07060-042
80 tR/tF 70
60
-6
-4
-2
0 2 JITTER (ps)
4
6
8
10
-40
-20
0 20 40 TEMPERATURE (C)
60
80
100
Figure 35. Random Jitter Histogram
Figure 36. Rise Time (tR)/Fall Time (tF) vs. Temperature
Rev. A | Page 15 of 32
07060-043
0 -8
50 -60
ADN8102 THEORY OF OPERATION
LOS_B RECEIVE EQUALIZATION Ix_B[3:0] EQ 2:1
ADN8102
TRANSMIT PRE-EMPHASIS
PE
RECEIVERS
Input Structure and Input Levels
Ox_B[3:0]
LB TRANSMIT PRE-EMPHASIS Ox_A[3:0] PE 2:1 RECEIVE EQUALIZATION EQ
LOS_A
Ix_A[3:0]
ADDR[1:0] SCL SDA RESET
CONTROL LOGIC
07060-003
EQ_A[1:0] PE_A[1:0] EQ_B[1:0] PE_B[1:0] ENA ENB
The ADN8102 receiver inputs incorporate 50 termination resistors, ESD protection, and a multizero transfer function equalizer that can be optimized for backplane or cable operation. Each channel also provides a programmable loss-of-signal (LOS) function that provides an interrupt that can be used to squelch or disable the associated output when the differential input voltage falls below the programmed threshold value. Each receive channel also provides a P/N inversion function that allows the user to swap the sign of the input signal path to eliminate the need for board-level crossovers in the receiver channel. Table 5 illustrates some, but not all, possible combinations of input supply voltages. Table 5. Common Input Voltage Levels
Configuration Low VTTI, AC-Coupled Input Single 1.8 V Supply 3.3 V Core Single 3.3 V Supply
VCC
Figure 37. Simplified Functional Block Diagram
INTRODUCTION
The ADN8102 is a quad bidirectional cable and backplane equalizer that provides both input equalization and output preemphasis on both the line card and cable sides of the device. The device supports full loopback and through connectivity of the two unidirectional half-links, each consisting of four differential signal pairs. The ADN8102 offers extensively programmable output levels and pre-emphasis as well as the ability to disable the output current. The receivers integrate a programmable, multizero equalizer transfer function that is optimized to compensate either typical backplane or typical cable losses. The I/O on-chip termination resistors are terminated to usersettable supplies to support dc coupling in a wide range of logic styles. The ADN8102 supports a wide core supply range; VCC can be set from 1.8 V to 3.3 V. These features, together with programmable output levels, allow for a wide range of dc- and ac-coupled I/O configurations.
VCC (V) 1.8 1.8 3.3 3.3
VTTI (V) 1.6 1.8 1.8 3.3
SIMPLIFIED RECEIVER INPUT CIRCUIT
VTTI RLN RP 52 IP IN R2 750 I1 VEE
07060-004
RLP
RN 52
R1 750
Q1 R3 1k Q2
Figure 38. Simplified Input Structure
Rev. A | Page 16 of 32
ADN8102
EQUALIZATION SETTINGS
The ADN8102 receiver incorporates a multizero transfer function continuous time equalizer that provides up to 22 dB of high frequency boost at 1.875 GHz to compensate up to 30 meters of CX4 cable or 40 inches of FR4 at 3.75 Gbps. The ADN8102 allows joint control of the equalizer transfer function of the four equalizer channels in a single port through the I2C control interface. Port A and Port B equalizer transfer functions are controlled via Register 0x80 and Register 0xA0, respectively. The equalizer transfer function allows independent control of the boost in two different frequency ranges for optimal matching with the loss shape of the user's channel (for example, skin-effect loss dominated or dielectric loss dominated). By default, the equalizer control is simplified to two independent maps of basic settings that provide nine settings, each optimized for CX4 cable and FR4 to ease programming for typical channels. The default state of the part selects the CX4 optimized equalization map for the IN_A[3:0] channels that interface with the cable and the FR4 optimized equalization map for the IN_B[3:0] channels that interface with the board. Full control of the equalizer is available via the I2C control interface by writing register bit MODE[0] = 1 at Address 0x0F. Table 6 summarizes the high frequency boost for each of the basic control settings and the typical length of CX4 cable and FR4 trace that each setting compensates. Setting the EQBY bit of the IN_A/IN_B configuration registers high sets the equalization to 1.5 dB of boost, which compensates 0 meters to 2 meters of CX4 or 0 inches to 10 inches of FR4. Setting the LUT SELECT bit = 1 (Bit 1 in the IN_Ax/IN_Bx FR4 control registers) allows the default map selection (CX4 or FR4 optimized) to be overwritten via the LUT FR4/CX4 bit (Bit 0) in the IN_Ax/IN_Bx FR4 control registers. Setting this bit high selects the FR4 optimized map, and setting it low selects the CX4 optimized map. These settings are set on a per channel basis (see Table 7 and Table 17). The user can also specify the boost in the mid frequency and high frequency ranges independently. This is done by writing to the IN_A/IN_B EQ1 control and IN_A/IN_B EQ2 control registers for the channel of interest. Each of these registers provides 32 settings of boost, with IN_A/IN_B EQ1 control setting the mid-frequency boost and IN_A/IN_B EQ2 control setting the high frequency boost. The IN_A/IN_B EQx control registers are ordered such that Bit 5 is a sign bit, and midlevel boost is centered on 0x00; setting Bit 5 low and increasing the LSBs results in decreasing boost, while setting Bit 5 high and increasing the LSBs results in increasing boost. The EQ CTL SRC bit (Bit 6) in the IN_A/IN_B EQ1 Control registers determines whether the equalization control for the channel of interest is selected from the optimized map or directly from the IN_A/IN_B EQx control registers (per port). Setting this bit high selects equalization control directly from the IN_A/IN_B EQx control registers, and setting it low selects equalization control from the selected optimized map.
Table 6. Receive Equalizer Boost vs. Setting (CX4 and FR4 Optimized Maps)
IN_Ax/IN_Bx Configuration, EQ[2:0] 01 1 21 3 4 51 6 71
1
Boost (dB) 10 12 14 17 19 20 21 22
Cable Optimized Typical CX4 Cable Length (Meters) 4 to 6 8 to 10 12 to 14 16 to 18 20 to 22 24 to 26 28 to 30 30 to 32
Boost (dB) 3.5 3.9 4.25 4.5 4.75 5.0 5.3 5.5
FR4 Optimized Typical FR4 Trace Length (Inches) 5 to 10 10 to 15 15 to 20 20 to 25 25 to 30 30 to 35 35 to 40 35 to 40
These EQ settings are also available via the external device pins, EQ_A[1:0] and EQ_B[1:0].
Table 7. Receive Configuration and Equalization Registers
Name IN_A/IN_B Configuration IN_A/IN_B EQ1 Control IN_A/IN_B EQ2 Control IN_Ax/IN_Bx FR4 Control Address 0x80, 0xA0 0x83, 0xA3 0x84, 0xA4 0x85, 0x8D, 0x95, 0x9D, 0xA5, 0xAD, 0xB5, 0xBD
Rev. A | Page 17 of 32
Bit 7
Bit 6 PNSWAP EQ CTL SRC
Bit 5 EQBY EQ1[5] EQ2[5]
Bit 4 EN EQ1[4] EQ2[4]
Bit 3
Bit 2 EQ[2] EQ1[2] EQ2[2]
Bit 1 EQ[1] EQ1[1] EQ2[1] LUT SELECT
Bit 0 EQ[0] EQ1[0] EQ2[0] LUT FR4/CX4
Default 0x30 0x00 0x00 0x00
EQ1[3] EQ2[3]
ADN8102
Loss of Signal/Signal Detect
An independent signal detect output is provided for all eight input ports of the device. The signal-detect function measures the low frequency amplitude of the signal at the receiver input and compares this measurement with a defined threshold level. If the measurement indicates that the input signal swing is smaller than the threshold for 250 s, the channel indicates a loss-of-signal event. Assertion and deassertion of the LOS signal occurs within 100 s of the event. The LOS-assert and LOS-deassert levels are set on a per channel basis through the I2C control interface, by writing to the IN_A/ IN_B LOS threshold and IN_A/IN_B LOS hysteresis registers, respectively. The recommended settings are IN_A/IN_B THRESH = 0x0C and IN_A/IN_B HYST = 0x0D. All ports are factory tested with these settings to ensure that an LOS event is asserted for single-ended dc input swings less than 20 mV and is deasserted for single-ended dc input swings greater than 225 mV. The LOS status for each individual channel can be accessed through the I2C control interface. The independent channel LOS status can be read from the IN_A/IN_B LOS status registers (Address 0x1F and Address 0x3F). The four LSBs of each register represent the current LOS status of each channel, with high representing an ongoing LOS event. The four MSBs of each register represent the historical LOS status of each channel, with high representing a LOS event at any time on a specific channel. The MSBs are sticky and remain high once asserted until cleared by the user by overwriting the bits to 0.
Recommended LOS Settings
Recommended settings for LOS are as follows: * * Set IN_A/IN_B THRESH to 0x0C for an assert voltage of 20 mV differential (40 mV p-p differential). Set IN_A/IN_B HYST to 0x0D for a deassert voltage of 225 mV differential (450 mV p-p differential).
LANE INVERSION
The input P/N inversion is a feature intended to allow the user to implement the equivalent of a board-level crossover in a much smaller area and without additional via impedance discontinuities that degrade the high frequency integrity of the signal path. The P/N inversion is available on a per port basis and is controlled through the I2C control interface. The P/N inversion is accomplished by writing to the PNSWAP bit (Bit 6) of the IN_A/IN_B configuration register (see Table 7) with low representing a noninverting configuration and high representing an inverting configuration. Note that using this feature to account for signal inversions downstream of the receiver requires additional attention when switching connectivity.
Table 8. LOS Threshold and Hysteresis Control Registers
Name IN_A/IN_B LOS Threshold IN_A/IN_B LOS Hysteresis Address 0x81, 0xA1 0x82, 0xA2 Bit 7 Bit 6 THRESH[6] HYST[6] Bit 5 THRESH[5] HYST[5] Bit 4 THRESH[4] HYST[4] Bit 3 THRESH[3] HYST[3] Bit 2 THRESH[2] HYST[2] Bit 1 THRESH[1] HYST[1] Bit 0 THRESH[0] HYST[0] Default 0x04 0x12
Table 9. LOS Status Registers
Name IN_A/IN_B LOS Status Address 0x1F, 0x3F Bit 7 STICKY LOS[3] Bit 6 STICKY LOS[2] Bit 5 STICKY LOS[1] Bit 4 STICKY LOS [0] Bit 3 REAL-TIME LOS[3] Bit 2 REAL-TIME LOS[2] Bit 1 REAL-TIME LOS[1] Bit 0 REAL-TIME LOS[0]
Rev. A | Page 18 of 32
ADN8102
LOOPBACK
The ADN8102 provides loopback on both input ports (Port A: cable interface input, Port B: line card interface input). The external loopback toggle pin, LB, controls the loopback of the Port B input only (board side loopback). When loopback is asserted, valid data continues to pass through the Port B link, but the Port B input signals are also shunted to the Port A output to allow testing and debugging without disrupting valid data. This loopback, as well as loopback of the Port A input (cable side loopback), can be programmed through the I2C interface. The loopbacks are controlled through the I2C interface by writing to Bit 0 and Bit 1 of the global configuration control register (Register 0x02).
CABLE SIDE LOOPBACK
RECEIVE EQUALIZATION Ix_B[3:0] EQ TRANSMIT PRE-EMPHASIS PE Ox_B[3:0] Ix_B[3:0]
Bit 1 represents loopback of the Port A inputs to the Port B outputs (cable side loopback). Bit 0 represents loopback of the Port B inputs to the Port A outputs (board side loopback), with high representing loopback for both bits. Bit 0 is also controlled through the LB pin with I2C data overwriting the pin state. Both input ports can be looped back simultaneously (full loopback) by writing high to both Bit 0 and Bit 1, but in this case, valid data is disrupted on each channel. Figure 39 illustrates the three loopback modes.
BOARD SIDE LOOPBACK
RECEIVE EQUALIZATION EQ TRANSMIT PRE-EMPHASIS PE Ox_B[3:0] Ix_B[3:0]
FULL LOOPBACK
RECEIVE EQUALIZATION EQ TRANSMIT PRE-EMPHASIS PE Ox_B[3:0]
LB TRANSMIT PRE-EMPHASIS Ox_A[3:0] PE RECEIVE EQUALIZATION EQ
LOS_A
LB TRANSMIT PRE-EMPHASIS RECEIVE EQUALIZATION EQ
LOS_A
LB TRANSMIT PRE-EMPHASIS RECEIVE EQUALIZATION EQ
LOS_A
Ix_A[3:0]
Ox_A[3:0]
PE
Ix_A[3:0]
Ox_A[3:0]
PE
Ix_A[3:0]
Figure 39. Loopback Modes of Operation
Table 10. Global Configuration Register, Loopback Controls
Name Global Configuration Control Address 0x02 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LB[1] Bit 0 LB[0] Default 0x00
Rev. A | Page 19 of 32
07060-005
ADDR[1:0] SCL SDA RESET
CONTROL LOGIC
EQ_A[1:0] PE_A[1:0] EQ_B[1:0] PE_B[1:0] ENA ENB
ADDR[1:0] SCL SDA RESET
CONTROL LOGIC
EQ_A[1:0] PE_A[1:0] EQ_B[1:0] PE_B[1:0] ENA ENB
ADDR[1:0] SCL SDA RESET
CONTROL LOGIC
EQ_A[1:0] PE_A[1:0] EQ_B[1:0] PE_B[1:0] ENA ENB
ADN8102
TRANSMITTERS
Output Structure and Output Levels
The ADN8102 transmitter outputs incorporate 50 termination resistors, ESD protection, and an output current switch. Each port provides control of both the absolute output level and the pre-emphasis output level. It should be noted that the choice of output level affects the output common-mode level. A 600 mV peak-to-peak differential output level with full pre-emphasis range requires an output termination voltage of 2.5 V or greater (VTTO, VCC 2.5 V). The output equalization is optimized for less than 1.75 Gbps operation but can be optimized for higher speed applications at up to 3.75 Gbps through the I2C control interface by writing to the DATA RATE bit (Bit 4) of the OUT_A/OUT_B configuration registers, with high representing 3.75 Gbps and low representing 1.75 Gbps. The PE CTL SRC bit (Bit 7) in the OUT_A/OUT_B Output Level Control 1 register determines whether the preemphasis and output current controls for the channel of interest are selected from the optimized map or directly from the OUT_A/ OUT_B Output Level Control[1:0] registers (per channel). Setting this bit high selects pre-emphasis control directly from the OUT_A/OUT_B Output Level Control[1:0] registers, and setting it low selects pre-emphasis control from the optimized map.
Tx SIMPLIFIED DIAGRAM ON-CHIP TERMINATION V3 VC V2 VP ESD VCC VTTO
Pre-Emphasis
The total output amplitude and pre-emphasis setting space is reduced to a single map of basic settings that provides seven settings of output equalization to ease programming for typical channels. The PE_A/PE_B[1:0] pins provide selections 0, 2, 4, and 6 of the seven pre-emphasis settings through toggle pin control, covering the entire range of settings at lower resolution. The full resolution of seven settings is available through the I2C interface by writing to Bits[2:0] (PE[2:0] of the OUT_A/OUT_B configuration registers) with I2C settings overriding the toggle pin control. Similar to the receiver settings, the ADN8102 allows joint control of all four channels in a transmit port. Table 11 summarizes the absolute output level, pre-emphasis level, and high frequency boost for each of the basic control settings and the typical length of the CX4 cable and FR4 trace that each setting compensates. Full control of the transmit output levels is available through the I2C control interface. This full control is achieved by writing to the OUT_A/OUT_B Output Level Control[1:0] registers for the channel of interest. Table 13 shows the supported output level settings of the OUT_A/OUT_B Output Level Control[1:0] registers. Register settings not listed in Table 13 are not supported by the ADN8102.
RP 50 V1 VN Q1 Q2
RN 50 OP ON
VEE
Figure 40. Simplified Output Structure
Table 11. Transmit Pre-Emphasis Boost and Overshoot vs. Setting
PE 01 1 21 3 41 5 61
1
Boost (dB) 0 2 3.5 4.9 6 7.4 9.5
Overshoot 0% 25% 50% 75% 100% 133% 200%
DC Swing (mV p-p diff) 800 800 800 800 800 600 400
Typical CX4 Cable Length (Meters) 0 to 2.5 2.5 to 5 5 to 7.5 7.5 to 10 10 to 12.5 15 to 17.5 20 to 22.5
Typical FR4 Trace Length (Inches) 0 to 5 0 to 5 10 to 15 10 to 15 15 to 20 20 to 25 25 to 30
These PE settings are also available via external device pins, PE_A[1:0] and PE_B[1:0].
Table 12. Output Configuration Registers
Name OUT_A/OUT_B Configuration OUT_A/OUT_B Output Level Control 1 OUT_A/OUT_B Output Level Control 0 Address 0xC0, 0xE0 0xC1, 0xE1 0xC2, 0xE2 Bit 7 PE CTL SRC Bit 6 Bit 5 EN Bit 4 Bit 3 Bit 2 DATA RATE PE[2] OUTx_OLEV1[6:0] OUTx_OLEV0[6:0] Bit 1 PE[1] Bit 0 PE[0] Default 0x20 0x40 0x40
Rev. A | Page 20 of 32
07060-006
IDC + IPE
ITOT
ADN8102
Table 13. Output Level Settings
VOD (mV) 50 50 50 50 50 50 50 100 100 100 100 100 100 100 150 150 150 150 150 150 150 200 200 200 200 200 200 200 250 250 250 250 250 250 250 300 300 300 300 300 300 300 350 350 350 350 350 350 350 400 400 400 400 400 400 400 VD Peak (mV) 50 150 250 350 450 550 650 100 200 300 400 500 600 700 150 250 350 450 550 650 750 200 300 400 500 600 700 800 250 350 450 550 650 750 850 300 400 500 600 700 800 900 350 450 550 650 750 850 950 400 500 600 700 800 900 1000 PE (dB) 0.00 9.54 13.98 16.90 19.08 20.83 22.28 0.00 6.02 9.54 12.04 13.98 15.56 16.90 0.00 4.44 7.36 9.54 11.29 12.74 13.98 0.00 3.52 6.02 7.96 9.54 10.88 12.04 0.00 2.92 5.11 6.85 8.30 9.54 10.63 0.00 2.50 4.44 6.02 7.36 8.52 9.54 0.00 2.18 3.93 5.38 6.62 7.71 8.67 0.00 1.94 3.52 4.86 6.02 7.04 7.96 ITOT (mA) 2 6 10 14 18 22 26 4 8 12 16 20 24 28 6 10 14 18 22 26 30 8 12 16 20 24 28 32 10 14 18 22 26 30 34 12 16 20 24 28 32 36 14 18 22 26 30 34 38 16 20 24 28 32 36 40 OUT_A/OUT_B Output Level Control 0 0x00 0x11 0x22 0x33 0x44 0x55 0x66 0x00 0x11 0x22 0x33 0x44 0x55 0x66 0x00 0x11 0x22 0x33 0x44 0x55 0x66 0x00 0x11 0x22 0x33 0x44 0x55 0x66 0x00 0x11 0x22 0x33 0x44 0x55 0x66 0x00 0x11 0x22 0x33 0x44 0x55 0x66 0x00 0x11 0x22 0x33 0x44 0x55 0x66 0x00 0x11 0x22 0x33 0x44 0x55 0x66
Rev. A | Page 21 of 32
OUT_A/OUT_B Output Level Control 1 0x81 0x81 0x81 0x81 0x81 0x81 0x81 0x91 0x91 0x91 0x91 0x91 0x91 0x91 0x92 0x92 0x92 0x92 0x92 0x92 0x92 0xA2 0xA2 0xA2 0xA2 0xA2 0xA2 0xA2 0xA3 0xA3 0xA3 0xA3 0xA3 0xA3 0xA3 0xB3 0xB3 0xB3 0xB3 0xB3 0xB3 0xB3 0xB4 0xB4 0xB4 0xB4 0xB4 0xB4 0xB4 0xC4 0xC4 0xC4 0xC4 0xC4 0xC4 0xC4
ADN8102
VOD (mV) 450 450 450 450 450 450 450 500 500 500 500 500 500 500 550 550 550 550 550 550 550 600 600 600 600 600 600 600 650 650 650 650 650 650 700 700 700 700 700 750 750 750 750 800 800 800 850 850 900 VD Peak (mV) 450 550 650 750 850 950 1050 500 600 700 800 900 1000 1100 550 650 750 850 950 1050 1150 600 700 800 900 1000 1100 1200 650 750 850 950 1050 1150 700 800 900 1000 1100 750 850 950 1050 800 900 1000 850 950 900 PE (dB) 0.00 1.74 3.19 4.44 5.52 6.49 7.36 0.00 1.58 2.92 4.08 5.11 6.02 6.85 0.00 1.45 2.69 3.78 4.75 5.62 6.41 0.00 1.34 2.50 3.52 4.44 5.26 6.02 0.00 1.24 2.33 3.30 4.17 4.96 0.00 1.16 2.18 3.10 3.93 0.00 1.09 2.05 2.92 0.00 1.02 1.94 0.00 0.97 0.00 ITOT (mA) 18 22 26 30 34 38 42 20 24 28 32 36 40 44 22 26 30 34 38 42 46 24 28 32 36 40 44 48 26 30 34 38 42 46 28 32 36 40 44 30 34 38 42 32 36 40 34 38 36 OUT_A/OUT_B Output Level Control 0 0x00 0x11 0x22 0x33 0x44 0x55 0x66 0x00 0x11 0x22 0x33 0x44 0x55 0x66 0x00 0x11 0x22 0x33 0x44 0x55 0x66 0x00 0x11 0x22 0x33 0x44 0x55 0x66 0x01 0x12 0x23 0x34 0x45 0x56 0x02 0x13 0x24 0x35 0x46 0x03 0x14 0x25 0x36 0x04 0x15 0x26 0x05 0x16 0x06 OUT_A/OUT_B Output Level Control 1 0xC5 0xC5 0xC5 0xC5 0xC5 0xC5 0xC5 0xD5 0xD5 0xD5 0xD5 0xD5 0xD5 0xD5 0xD6 0xD6 0xD6 0xD6 0xD6 0xD6 0xD6 0xE6 0xE6 0xE6 0xE6 0xE6 0xE6 0xE6 0xE6 0xE6 0xE6 0xE6 0xE6 0xE6 0xE6 0xE6 0xE6 0xE6 0xE6 0xE6 0xE6 0xE6 0xE6 0xE6 0xE6 0xE6 0xE6 0xE6 0xE6
Rev. A | Page 22 of 32
ADN8102
High Current Setting and Output Level Shift
In low voltage applications, users must pay careful attention to both the differential and common-mode signal levels (see Figure 41 and Table 14 and Table 15. Failure to understand the implications of signal level and choice of ac or dc coupling almost certainly leads to transistor saturation and poor transmitter performance.
VTTO VOCM VH VOD VOCM VL
TxHeadroom
The TxHeadroom register (Register 0x23) allows configuration of the individual transmitters for extra headroom at the output for high current applications. The bits in this register are active high (default) and are one per output (see Table 17). Setting a bit high puts the respective transmitter in a configuration for extra headroom and setting a bit low does not provide extra headroom. The TxHeadroom bits should only be set high when VCC exceeds the value listed in Table 14 for a given output swing.
VEE
Figure 41. Simplified Output Voltage Levels Diagram
Rev. A | Page 23 of 32
07060-007
VOD p-p = 2 x VOD
ADN8102
Signal Levels and Common-Mode Shift for DC- and AC-Coupled Outputs
Table 14.
Output Levels and Output Compliance AC-Coupled Transmitter DC-Coupled Transmitter VL VL Min VD VH VH PE dVOCM VH Peak Peak dVOCM VH Peak Peak VL VOD ITOT Peak PE VL VL (V) (V) (mV) (mA) (mV) Boost (dB) (mV) (V) (V) (V) (mV) (V) (V) (V) (V) TxHeadroom = 0 Max Min Min VCC - VL VCC VL (V) (V) (V) TxHeadroom = 1 Max VCC - VL Min (V) VCC (V)
VTTO and VCC = 3.3 V 200 8 200 1.00 200 12 300 1.50 200 16 400 2.00 200 20 500 2.50 200 24 600 3.00 200 28 700 3.50 200 32 800 4.00 300 12 300 1.00 300 16 400 1.33 300 20 500 1.67 300 24 600 2.00 300 28 700 2.33 300 32 800 2.67 300 36 900 3.00 400 16 400 1.00 400 20 500 1.25 400 24 600 1.50 400 28 700 1.75 400 32 800 2.00 400 36 900 2.25 400 40 1000 2.50 600 24 600 1.00 600 28 700 1.17 600 32 800 1.33 600 36 900 1.50 600 40 1000 1.67 600 44 1200 1.83 600 48 1400 2.00 VTTO and VCC = 1.8 V 1 200 8 200 1.00 200 12 300 1.50 200 16 400 2.00 200 20 500 2.50 200 24 600 3.00 300 12 300 1.00 300 16 400 1.33 300 20 500 1.67 300 24 600 2.00 300 28 700 2.33 400 16 400 1.00 400 20 500 1.25 400 24 600 1.50 400 28 700 1.75 400 32 800 2.00 600 24 600 1.00
1
0.00 3.52 6.02 7.96 9.54 10.88 12.04 0.00 2.50 4.44 6.02 7.36 8.52 9.54 0.00 1.94 3.52 4.86 6.02 7.04 7.96 0.00 1.34 2.50 3.52 4.44 5.26 6.02 0.00 3.52 6.02 7.96 9.54 0.00 2.50 4.44 6.02 7.36 0.00 1.94 3.52 4.86 6.02 0.00
200 300 400 500 600 700 800 300 400 500 600 700 800 900 400 500 600 700 800 900 1000 600 700 800 900 1000 1100 1200 200 300 400 500 600 300 400 500 600 700 400 500 600 700 800 600
3.2 3.1 3 2.9 2.8 2.7 2.6 3.15 3.05 2.95 2.85 2.75 2.65 2.55 3.1 3 2.9 2.8 2.7 2.6 2.5 3 2.9 2.8 2.7 2.6 2.5 2.4 1.7 1.6 1.5 1.4 1.3 1.65 1.55 1.45 1.35 1.25 1.6 1.5 1.4 1.3 1.2 1.5
3 2.9 2.8 2.7 2.6 2.5 2.4 2.85 2.75 2.65 2.55 2.45 2.35 2.25 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2.4 2.3 2.2 2.1 2 1.9 1.8 1.5 1.4 1.3 1.2 1.1 1.35 1.25 1.15 1.05 0.95 1.2 1.1 1 0.9 0.8 0.9
3.2 3.15 3.1 3.05 3 2.95 2.9 3.15 3.1 3.05 3 2.95 2.9 2.85 3.1 3.05 3 2.95 2.9 2.85 2.8 3 2.95 2.9 2.85 2.8 2.75 2.7 1.7 1.65 1.6 1.55 1.5 1.65 1.6 1.55 1.5 1.45 1.6 1.55 1.5 1.45 1.4 1.5
3 2.85 2.7 2.55 2.4 2.25 2.1 2.85 2.7 2.55 2.4 2.25 2.1 1.95 2.7 2.55 2.4 2.25 2.1 1.95 1.8 2.4 2.25 2.1 1.95 1.8 1.65 1.5 1.5 1.35 1.2 1.05 0.9 1.35 1.2 1.05 0.9 0.75 1.2 1.05 0.9 0.75 0.6 0.9
100 150 200 250 300 350 400 150 200 250 300 350 400 450 200 250 300 350 400 450 500 300 350 400 450 500 550 600 100 150 200 250 300 150 200 250 300 350 200 250 300 350 400 300
3.3 3.25 3.2 3.15 3.1 3.05 3 3.3 3.25 3.2 3.15 3.1 3.05 3 3.3 3.25 3.2 3.15 3.1 3.05 3 3.3 3.25 3.2 3.15 3.1 3.05 3 1.8 1.75 1.7 1.65 1.6 1.8 1.75 1.7 1.65 1.6 1.8 1.75 1.7 1.65 1.6 1.8
3.1 3.05 3 2.95 2.9 2.85 2.8 3 2.95 2.9 2.85 2.8 2.75 2.7 2.9 2.85 2.8 2.75 2.7 2.65 2.6 2.7 2.65 2.6 2.55 2.5 2.45 2.4 1.6 1.55 1.5 1.45 1.4 1.5 1.45 1.4 1.35 1.3 1.4 1.35 1.3 1.25 1.2 1.2
3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8
3.1 3 2.9 2.8 2.7 2.6 2.5 3 2.9 2.8 2.7 2.6 2.5 2.4 2.9 2.8 2.7 2.6 2.5 2.4 2.3 2.7 2.6 2.5 2.4 2.3 2.2 2.1 1.6 1.5 1.4 1.3 1.2 1.5 1.4 1.3 1.2 1.1 1.4 1.3 1.2 1.1 1 1.2
2.225 2.225 2.225 2.225 2.225 2.225 2.225 2.225 2.225 2.225 2.225 2.225 2.225 2.225 2.225 2.225 2.225 2.225 2.225 2.225 2.225 2.1 2.225 2.225 2.225 2.225 2.1 2.1 0.725 0.725 0.725 0.725 0.725 0.725 0.725 0.725 0.725 0.725 0.725 0.725 0.725 0.725 0.725 0.6
1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1
1.8 1.8 1.8 1.8 1.8 1.9 1.9 1.8 1.8 1.8 1.8 1.8 1.9 1.9 1.8 1.8 1.8 1.8 1.8 1.9 1.9 1.9 1.9 1.9 1.9 1.9 1.9 1.9 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.9
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5
1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA
2 2 2 2 2 2.2 2.2 2 2 2 2 2 2.2 2.2 2 2 2 2 2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA
TxHeadroom = 1 is not an option at VTTO and VCC = 1.8 V.
Rev. A | Page 24 of 32
ADN8102
Table 15. Symbol Definitions for Output Levels vs. Setting
Symbol VOD VOD p-p dVOCM_DC-COUPLED dVOCM_AC-COUPLED IDC IPE ITOT VH VL Formula 25 x IDC 25 x IDC x 2 = 2 x VOD 25 x ITOT/2 = VOD p-p/4 + (IPE/2 x 25) 50 x ITOT/2 = VOD p-p/2 + (IPE/2 x 50) VOD/RTERM -- IDC + IPE VTTO - dVOCM + VOD/2 VTTO - dVOCM - VOD/2 Definition Peak differential output voltage Peak-to-peak differential output voltage Output common-mode shift Output common-mode shift Output current that sets output level Output current used for PE Total transmitter output current Maximum single-ended output voltage Minimum single-ended output voltage
SELECTIVE SQUELCH AND DISABLE
Each transmitter is equipped with output disable and output squelch controls. Disable is a full power-down state: the transmitter current is reduced to zero and the output pins pull up to VTTO, but there is a delay of approximately 1 s associated with re-enabling the transmitter. The output disable control is accessed through the EN bit (Bit 5) of the OUT_A/OUT_B configuration registers through the I2C control interface. Squelch is not a full power-down state but a state in which only the output current is reduced to zero and the output pins pull up to VTTO, and there is a much smaller delay to bring back the output current. The output squelch and the output disable control can both be accessed through the OUT_A/OUT_B squelch control registers, with the top nibble representing the squelch control for one entire output port and the bottom nibble representing the output disable for one entire output port. The ports are disabled or squelched by writing 0s to the corresponding nibbles. The ports are enabled by writing all 1s, which is the default setting. For example, to squelch Port A, Register 0xC3 must be set to 0x0F. The entire nibble must be written to all 0s for this functionality.
Table 16. Squelch Programming
Name OUT_A/ OUT_B Squelch Control Address 0xC3, 0xE3 Data SQUELCH[3:0] DISABLE[3:0] Default 0xFF
Rev. A | Page 25 of 32
ADN8102 I2C CONTROL INTERFACE
SERIAL INTERFACE GENERAL FUNCTIONALITY
The ADN8102 register set is controlled through a 2-wire I2C interface. The ADN8102 acts only as an I2C slave device. Therefore, the I2C bus in the system needs to include an I2C master to configure the ADN8102 and other I2C devices that may be on the bus. Data transfers are controlled using the two I2C wires: the SCL input clock pin and the SDA bidirectional data pin. The ADN8102 I2C interface can be run in the standard (100 kHz) and fast (400 kHz) modes. The SDA line only changes value when the SCL pin is low with two exceptions. To indicate the beginning or continuation of a transfer, the SDA pin is driven low while the SCL pin is high, and to indicate the end of a transfer, the SDA line is driven high while the SCL line is high. Therefore, it is important to control the SCL clock to toggle only when the SDA line is stable, unless indicating a start, repeated start, or stop condition. 7. 8. 9a. 9b. Send the data (eight bits) to be written to the register whose address was set in Step 5. This transfer should be MSB first. Wait for the ADN8102 to acknowledge the request. Send a stop condition (while holding the SCL line high, pull the SDA line high) and release control of the bus. Send a repeated start condition (while holding the SCL line high, pull the SDA line low) and continue with Step 2 in this procedure to perform another write. Send a repeated start condition (while holding the SCL line high, pull the SDA line low) and continue with Step 2 of the read procedure (in the I2C Interface Data Transfers-- Data Read section) to perform a read from another address. Send a repeated start condition (while holding the SCL line high, pull the SDA line low) and continue with Step 8 of the read procedure (in the I2C Interface Data Transfers-- Data Read section) to perform a read from the same address set in Step 5.
9c.
9d.
I2C INTERFACE DATA TRANSFERS--DATA WRITE
To write data to the ADN8102 register set, a microcontroller, or any other I2C master, needs to send the appropriate control signals to the ADN8102 slave device. The steps that need to be completed are listed as follows, where the signals are controlled by the I2C master, unless otherwise specified. A diagram of the procedure can be seen in Figure 42. 1. 2. Send a start condition (while holding the SCL line high, pull the SDA line low). Send the ADN8102 part address (seven bits) whose upper five bits are the static value 10010b and whose lower two bits are controlled by the ADDR[1:0] input pins. This transfer should be MSB first. Send the write indicator bit (0). Wait for the ADN8102 to acknowledge the request. Send the register address (eight bits) to which data is to be written. This transfer should be MSB first. Wait for the ADN8102 to acknowledge the request.
SCL
Figure 42 shows the ADN8102 write process. The SCL signal is shown along with a general write operation and a specific example. In the example, Data 0x92 is written to Address 0x6D of an ADN8102 part with a part address of 0x4B. The part address is seven bits wide. The upper five bits of the ADN8102 are internally set to 10010b. The lower two bits are controlled by the ADDR[1:0] pins. In this example, the bits controlled by the ADDR[1:0] pins are set to 11b. In Figure 42, the corresponding step number is visible in the circle under the waveform. The SCL line is driven by the I2C master and never by the ADN8102 slave. As for the SDA line, the data in the shaded polygons is driven by the ADN8102, whereas the data in the nonshaded polygons is driven by the I2C master. The end phase case shown is that of Step 9a. Note that the SDA line only changes when the SCL line is low, except for the case of sending a start, stop, or repeated start condition, Step 1 and Step 9 in this case.
3. 4. 5. 6.
GENERAL CASE
SDA START FIXED PART ADDR ADDR [1:0] R/W ACK REGISTER ADDR ACK DATA ACK STOP
EXAMPLE
SDA 1 2 2 3 4 5 6 7 8 9a
07060-008
Figure 42. I2C Write Diagram
Rev. A | Page 26 of 32
ADN8102
I2C INTERFACE DATA TRANSFERS--DATA READ
To read data from the ADN8102 register set, a microcontroller, or any other I2C master, needs to send the appropriate control signals to the ADN8102 slave device. The steps that need to be completed are listed as follows, where the signals are controlled by the I2C master, unless otherwise specified. A diagram of the procedure can be seen in Figure 43. 1. 2. Send a start condition (while holding the SCL line high, pull the SDA line low). Send the ADN8102 part address (seven bits) whose upper five bits are the static value 10010b and whose lower two bits are controlled by the input pins ADDR[1:0]. This transfer should be MSB first. Send the write indicator bit (0). Wait for the ADN8102 to acknowledge the request. Send the register address (eight bits) from which data is to be read. This transfer should be MSB first. The register address is kept in memory in the ADN8102 until the part is reset or the register address is written over with the same procedure (Step 1 to Step 6). Wait for the ADN8102 to acknowledge the request. Send a repeated start condition (while holding the SCL line high, pull the SDA line low). Send the ADN8102 part address (seven bits) whose upper five bits are the static value 10010b and whose lower two bits are controlled by the input pins ADDR[1:0]. This transfer should be MSB first. Send the read indicator bit (1). Wait for the ADN8102 to acknowledge the request. The ADN8102 then serially transfers the data (eight bits) held in the register indicated by the address set in Step 5. Acknowledge the data.
SCL
13a. 13b.
13c.
13d.
Send a stop condition (while holding the SCL line high, pull the SDA line high) and release control of the bus. Send a repeated start condition (while holding the SCL line high, pull the SDA line low) and continue with Step 2 of the write procedure (in the I2C Interface Data Transfers--Data Write section) to perform a write. Send a repeated start condition (while holding the SCL line high, pull the SDA line low) and continue with Step 2 of this procedure to perform a read from a another address. Send a repeated start condition (while holding the SCL line high, pull the SDA line low) and continue with Step 8 of this procedure to perform a read from the same address.
3. 4. 5.
6. 7. 8.
Figure 43 shows the ADN8102 read process. The SCL signal is shown along with a general read operation and a specific example. In the example, Data 0x49 is read from Address 0x6D of an ADN8102 part with a part address of 0x4B. The part address is seven bits wide. The upper five bits of the ADN8102 are internally set to 10010b. The lower two bits are controlled by the ADDR[1:0] pins. In this example, the bits controlled by the ADDR[1:0] pins are set to 11b. In Figure 43, the corresponding step number is visible in the circle under the waveform. The SCL line is driven by the I2C master and never by the ADN8102 slave. As for the SDA line, the data in the shaded polygons is driven by the ADN8102, whereas the data in the nonshaded polygons is driven by the I2C master. The end phase case shown is that of Step 13a. Note that the SDA line changes only when the SCL line is low, except for the case of sending a start, stop, or repeated start condition, as in Step 1, Step 7, and Step 13. In Figure 43, A is the same as ACK in Figure 42. Equally, Sr represents a repeated start where the SDA line is brought high before SCL is raised. SDA is then dropped while SCL is still high.
9. 10. 11. 12.
GENERAL CASE
SDA START FIXED PART ADDR
ADDR R/ [1:0] W
A
REGISTER ADDR
A Sr
FIXED PART ADDR
ADDR R/ [1:0] W A
DATA
A
STOP
EXAMPLE
SDA 1 2 2 3 4 5 6 7 8 8 9 10 11 12 13a
07060-009
Figure 43. I2C Read Diagram
Rev. A | Page 27 of 32
ADN8102 PCB DESIGN GUIDELINES
Proper RF PCB design techniques must be used for optimal performance.
TRANSMISSION LINES
Use of 50 transmission lines is required for all high frequency input and output signals to minimize reflections. It is also necessary for the high speed pairs of differential input traces to be matched in length, as well as the high speed pairs of differential output traces, to avoid skew between the differential traces.
POWER SUPPLY CONNECTIONS AND GROUND PLANES
Use of one low impedance ground plane is recommended. The VEE pins should be soldered directly to the ground plane to reduce series inductance. If the ground plane is an internal plane and connections to the ground plane are made through vias, multiple vias can be used in parallel to reduce the series inductance. The exposed pad should be connected to the VEE plane using plugged vias so that solder does not leak through the vias during reflow. Use of a 10 F electrolytic capacitor between VCC and VEE is recommended at the location where the 3.3 V supply enters the printed circuit board (PCB). It is recommended that 0.1 F and 1 nF ceramic chip capacitors be placed in parallel at each supply pin for high frequency power supply decoupling. When using 0.1 F and 1 nF ceramic chip capacitors, they should be placed between the IC power supply pins (VCC, VTTI, and VTTO) and VEE, as close as possible to the supply pins. By using adjacent power supply and GND planes, excellent high frequency decoupling can be realized by using close spacing between the planes. This capacitance is given by CPLANE = 0.88r x A/d (pF) where: r is the dielectric constant of the PCB material. A is the area of the overlap of power and GND planes (cm2). d is the separation between planes (mm). For FR4, r = 4.4, and 0.25 mm spacing, C 15 pF/cm2.
SOLDERING GUIDELINES FOR CHIP SCALE PACKAGE
The lands on the LFCSP are rectangular. The PCB pad for these should be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. Center the land on the pad, which ensures that the solder joint size is maximized. The bottom of the chip scale package has a central exposed pad. The pad on the PCB should be at least as large as this exposed pad. The user must connect the exposed pad to VEE using plugged vias so that solder does not leak through the vias during reflow. This ensures a solid connection from the exposed pad to VEE.
Rev. A | Page 28 of 32
ADN8102 REGISTER MAP
Table 17. I2C Register Definitions
Name Reset Global Configuration Control Mode TxHeadroom IN_A Configuration IN_A LOS Threshold IN_A LOS Hysteresis IN_A LOS Status 1 IN_A EQ1 Control IN_A EQ2 Control IN_A0 FR4 Control IN_A1 FR4 Control IN_A2 FR4 Control IN_A3 FR4 Control IN_B Configuration IN_B LOS Threshold IN_B LOS Hysteresis IN_B LOS Status1 IN_B EQ1 Control IN_B EQ2 Control IN_B3 FR4 Control IN_B2 FR4 Control IN_B1 FR4 Control IN_B0 FR4 Control Address 0x00 0x02 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LB[1] Bit 0 RESET LB[0] Default 0x00
0x0F 0x23 0x80 0x81 0x82 0x1F 0x83 0x84 0x85 0x8D 0x95 0x9D 0xA0 0xA1 0xA2 0x3F 0xA3 0xA4 0xA5 0xAD 0xB5 0xBD
TxH_B3
TxH_B2 PNSWAP THRESH[6] HYST[6]
TxH_B1 EQBY THRESH[5] HYST[5] STICKY LOS[1] EQ1[5] EQ2[5]
TxH_B0 EN THRESH[4] HYST[4] STICKY LOS[0] EQ1[4] EQ2[4]
TxH_A3
TxH_A2 EQ[2] THRESH[2] HYST[2] REAL-TIME LOS[2] EQ1[2] EQ2[2]
MODE[1] TxH_A1 EQ[1] THRESH[1] HYST[1] REAL-TIME LOS[1] EQ1[1] EQ2[1] LUT SELECT LUT SELECT LUT SELECT LUT SELECT EQ[1] THRESH[1] HYST[1] REAL-TIME LOS[1] EQ1[1] EQ2[1] LUT SELECT LUT SELECT LUT SELECT LUT SELECT
MODE[0] TxH_A0 EQ[0] THRESH[0] HYST[0] REAL-TIME LOS[0] EQ1[0] EQ2[0] LUT FR4/CX4 LUT FR4/CX4 LUT FR4/CX4 LUT FR4/CX4 EQ[0] THRESH[0] HYST[0] REAL-TIME LOS[0] EQ1[0] EQ2[0] LUT FR4/CX4 LUT FR4/CX4 LUT FR4/CX4 LUT FR4/CX4
0x00 0x00 0x30 0x04 0x12
THRESH[3] HYST[3] REAL-TIME LOS[3] EQ1[3] EQ2[3]
STICKY LOS[3]
STICKY LOS[2] EQ CTL SRC
0x00 0x00 0x00 0x00 0x00 0x00 0x30 0x04 0x12
PNSWAP THRESH[6] HYST[6] STICKY LOS [3] STICKY LOS [2] EQ CTL SRC
EQBY THRESH[5] HYST[5] STICKY LOS [1] EQ1[5] EQ2[5]
EN THRESH[4] HYST[4] STICKY LOS[0] EQ1[4] EQ2[4] THRESH[3] HYST[3] REAL-TIME LOS[3] EQ1[3] EQ2[3]
EQ[2] THRESH[2] HYST[2] REAL-TIME LOS[2] EQ1[2] EQ2[2]
0x00 0x00 0x00 0x00 0x00 0x00
Rev. A | Page 29 of 32
ADN8102
Name OUT_A Configuration OUT_A Output Level Control 1 OUT_A Output Level Control 0 OUT_A Squelch Control OUT_B Configuration OUT_B Output Level Control 1 OUT_B Output Level Control 0 OUT_B Squelch Control
1
Address 0xC0 0xC1
Bit 7
Bit 6
Bit 5 EN
Bit 4 DATA RATE
Bit 3
Bit 2 PE[2]
Bit 1 PE[1]
Bit 0 PE[0]
Default 0x20 0x40
PE CTL SRC
OUTA_OLEV1[6:0]
0xC2
OUTA_OLEV0[6:0]
0x40
0xC3
SQUELCH[3:0]
DISABLE[3:0]
0xFF
0xE0 0xE1 PE CTL SRC
EN
DATA RATE
PE[2] OUTB_OLEV1[6:0]
PE[1]
PE[0]
0x20 0x40
0xE2
OUTB_OLEV0[6:0]
0x40
0xE3
SQUELCH[3:0]
DISABLE[3:0]
0xFF
Read-only register.
Rev. A | Page 30 of 32
ADN8102 OUTLINE DIMENSIONS
9.00 BSC SQ 0.60 MAX 0.60 MAX
49 48
0.30 0.25 0.18
64 1
PIN 1 INDICATOR
PIN 1 INDICATOR
TOP VIEW
8.75 BSC SQ
EXPOSED PAD
(BOTTOM VIEW)
*6.15 6.00 SQ 5.85
0.50 0.40 0.30
33 32
17 16
1.00 0.85 0.80
12 MAX
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.50 BSC 0.20 REF
7.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
080108-B
SEATING PLANE
*COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 EXCEPT FOR EXPOSED PAD DIMENSION
Figure 44. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 9 mm x 9 mm Body, Very Thin Quad (CP-64-2) Dimensions shown in millimeters
ORDERING GUIDE
Model ADN8102ACPZ 1 ADN8102ACPZ-R71 ADN8102-EVALZ1
1
Temperature Range -40C to +85C -40C to +85C
Package Description 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board
Package Option CP-64-2 CP-64-2
Z = RoHS Compliant Part.
Rev. A | Page 31 of 32
ADN8102 NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
(c)2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07060-0-8/08(A)
Rev. A | Page 32 of 32

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